1. Field of the Invention
The invention relates to an edge multiplier circuit. A circuit of this type can be used, for example, to obtain several phase-shifted clock signals from the same reference clock signal. A circuit of this type can also be used to obtain a clock signal with a higher frequency than a reference clock signal.
2. Description of Related Art
French patent application FR2658015 (U.S. Pat. No. 5,260,608, U.S. Pat. No. 5,548,235 and U.S. Pat. No. 5,838,178 in the United States) describes a phase-locked circuit that makes it possible to produce a frequency multiplier. Compared to known circuits of the VCO, or voltage-controlled type, this circuit has the advantage of a short response time and good noise immunity. A delay circuit within it is driven by the output signal of a phase comparator between the input signal and the output signal of the delay circuit. The delay circuit within it is constituted by a number N of cascading cells such that the control signal controls an elementary delay increment Te of each cell. Since the control signal drives the N cells simultaneously, the minimum delay increment of the delay circuit is equal to N times the elementary delay increment Te of each cell. The delay circuit in this prior art makes it possible to correct a phase error between its input and its output with a precision of N times Te at best.
One object of the present invention is to correct a phase error between the input and the output of a delay circuit with better precision than N times Te. This offers an advantage in attaining high frequencies, even though minimum value of an elementary delay increment Te is necessarily limited by the production technology of the circuit. In one solution of the present invention, the output signal of the phase comparator does not drive the N cells simultaneously, but actuates each cell separately.
The proposed solution is not obvious because driving all of the cells simultaneously guarantees that the duty cycle of the signal is maintained. In fact, it is noted that in a delay circuit of the prior art, incrementing the delay of only one cell at a time poses a problem. For a phase error of Te, before correction, the output signal of each cell has a phase error of n times Te/N relative to the ideal phase, n varying from 1 for the first cell at the input of the delay circuit, to N for the last cell at the output of the delay circuit.
A command for successively incrementing each cell in cascading order is not satisfactory. A correction of Te in the first cell produces a phase error equal to (Nxe2x88x921)Te/N relative to the ideal phase, followed by a phase error equal to (Nxe2x88x92n)Te/N in each cell up to the last one, for which the phase error equal to (Nxe2x88x92N)/Te/N is null. In a frequency multiplier in which the output signals of all or some of the cells are combined, this can have the consequence of modifying the duty cycle of (Nxe2x88x921)Te/N. The phase error results in the obtainment of a phase-shifted clock signal starting with an nth cell. The phenomenon is further amplified for a phase error throughout the delay circuit, greater than Te.
A command for successively incrementing each cell in reverse cascading order is not satisfactory, either. Starting with the center cell of the delay circuit carries the problem over to both the preceding group of cells and the following group of cells, adding to this the problem of choosing which group of cells to use for a subsequent correction.
The object of the invention is to create an edge multiplier circuit using a delay circuit constituted by cells connected in cascade, phase-looped back to its input, while avoiding the aforementioned drawbacks of the prior art.
The subject of the invention is a method for determining an order of cells to be delayed in a chain of N phase-looped delay cells. The method comprises:
a first action loop for values j varying from 1 to N, each corresponding to a total delay equal to j times an elementary delay of a cell, to be applied to the chain of N delay cells, an action of the first loop comprising:
a second action loop for values i varying from 1 to N, each corresponding to a rank of a cell in said chain, an action of the second loop calculating a delay error output from the cell of rank i relative to an ideal delay that distributes the total delay of the chain equally to each cell, in such a way that:
a first value of said error is calculated prior to activating any additional elementary delay of the cell of rank i;
a second value of said error is calculated if the first value is higher than a predetermined threshold, after activating an additional elementary delay of said cell of rank i, said rank i completing said order to be determined.
The order determined by the method according to the invention makes it possible to produce an edge multiplier circuit in which an additional elementary delay is progressively applied to a new cell in the order determined, in order to minimize the error output from each cell relative to an ideal delay distributed equally among all the cells. The implementation of the method for values of N varying from 3 to 20 and beyond made it possible to observe a maximum error equivalent to the elementary delay.